Pii: S0026-2692(99)00047-6

Novel CMOS realizations of the second and the third generation current conveyors based on the use of the current conveyor of the first generation are given. The simulations show that these circuits have an excellent performance and an exceptional bandwidth. q 1999 Elsevier Science Ltd. All rights reserved. Keywords: Current conveyors; CMOS realizations 1. Introduction Since its conception, the current conveyor has proven to be an exceptionally versatile current mode building block that can be implemented as several functional circuits, a current amplifier, current integrator and current summer [1–14]. The current conveyor is a three-port network with a describing matrix of the form VX IY IZ 664 775 ˆ 0 1 0 m 0 0 K 0 0 664 775 IX VY VZ 664 775 …1† where m determines the nature of the conveyor. If mˆ 1, the conveyor is a first generation current conveyor (CCI), if mˆ 0, the conveyor is a second generation current conveyor (CCII) and if m ˆ 21, the conveyor is a third generation current conveyor (CCIII). K determines the polarity of the conveyor. If K ˆ 1, the conveyor is a CC1 and if K ˆ 21, the conveyor is a CC2. The purpose of this article is to give new CMOS realizations for the CCII and the CCIII with a wide operating range and excellent frequency response. The CCI, introduced by Smith and Sedra [1], is shown in Fig. 1. In the circuit shown, a perfect matching between the transistors M1–M2 and M3–M4 is necessary for the proper operation of the circuit [2]. Two local feedback actions across the drains of transistors were responsible for the remarkable performance of this circuit despite its simplicity. The circuit conveys the voltage from Y to X, and the current from X to Y and Z, which offers a simplicity in use and a considerable frequency response giving birth to the current mode approach in the analog circuit design. Several applications were then introduced in the literature [2–9]. The key performance features of current-mode signal processing are wideband capability and a wide dynamic range under low-power operation. To exploit such potentials of current-mode signal processing, the CCII derived from the CCI reported in Ref. [2] (see Fig. 2) is based on the translinear loop and has prototyped many innovative designs that are simple and offer an excellent current following action over a wide bandwidth. However, it suffers from gain inaccuracy due to area mismatch between the input and the output transistors of the current and from the relatively low output resistance at the node Z. Brunn [10] employs a Floating Current Source (FCS) configured as CCII2 in order to obtain an accurate current following action which is unaffected by area mismatch. However, this requires matched PMOS and NMOS pairs in the voltage-follower section. Therefore, the voltage following action is inaccurate and there is a DC offset. A very promising technique to implement CCII consists of a feedback-stabilized voltage. This technique employs a high open-loop amplification in order to reduce the DC offset and to reduce the input resistance of the CCII. Several accurate implementations in the literature have followed this op-amp-based architecture [15]. However, these circuits have always suffered from an inaccurate current following action especially at high Microelectronics Journal 30 (1999) 1231–1239 Microelectronics Journal 0026-2692/99/$ see front matter q 1999 Elsevier Science Ltd. All rights reserved. PII: S0026-2692(99)00047-6 * Corresponding author. Tel.: 1 20-02-572-8564; fax: 1 20-02-5723486. E-mail address: [email protected] (A.M. Soliman) www.elsevier.com/locate/mejo